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IEICE Trans

Haopeng MENG

Nested-Pipeline Delta-Stepping Scalable FPGA Accelerator for Parallel Single-Source Shortest Path with High-Level Synthesis
Haopeng MENG Kazutoshi WAKABAYASHI Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3  pp. 563-570
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
SSSP, delta-stepping, FPGA, high-level synthesis, C++ based design, 
 Summary | Full Text:PDF