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IEICE Trans

Debatosh DEBNATH

A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5  pp. 932-940
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
three-level networks, AND-EXOR, NP-equivalence, coordinate representation, µ-equivalence, spectral method, logic minimization, 
 Summary | Full Text:PDF
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3443-3450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesis, Boolean matching, cell-library binding, technology mapping, canonical form, 
 Summary | Full Text:PDF
Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3332-3341
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
AND-EXOR, Reed-Muller expression, FPRM, exact minimization, incompletely specified function, 
 Summary | Full Text:PDF
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1492-1500
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
three-level network, logic minimization, adder, programmable logic, 
 Summary | Full Text:PDF
Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3134-3140
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
Boolean matching, technology mapping, variable permutation, P-equivalence, 
 Summary | Full Text:PDF
Minimization of AND-OR-EXOR Three-Level Networks with AND Gate Sharing
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 1001-1008
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
three-level networks, AND-EXOR, logic minimization, complexity of logic networks, NP-equivalence, 
 Summary | Full Text:PDF
Generalized Reed-Muller Expressions: Complexity and an Exact Minimization Algorithm
Tsutomu SASAO Debatosh DEBNATH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12  pp. 2123-2130
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
AND-EXOR, Reed-Muller expression, complexity of logic networks, logic minimization, binary decision diagrams, easily testable networks, 
 Summary | Full Text:PDF