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IEICE Trans

David CLARINO

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis
David CLARINO Naoya ASADA Atsushi MATSUO Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/04/01
Vol. E108-D  No. 4  pp. 320-329
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
relative-phase Toffoli gates (RTOF), circuit optimization, LUT, quantum circuit synthesis, 
 Summary | Full Text:PDF
Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate
David CLARINO Shohei KURODA Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/01/01
Vol. E108-A  No. 1  pp. 1-10
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
relative-phase Toffoli gates (RTOF), S gate, circuit optimization, 
 Summary | Full Text:PDF