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IEICE Trans

Chunhong CHEN

Timing Driven Gate Duplication in Technology Independent Phase
Ankur SRIVASTAVA Chunhong CHEN Majid SARRAFZADEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2673-2680
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
gate duplication, logic synthesis, delay optimization, technology mapping, 
 Summary | Full Text:PDF