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IEICE Trans

Chung Len LEE

Fault Analysis on (K+1)-Valued PLA Structure Logic Circuits
Hui Min WANG Chung Len LEE Jwu E CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 1001-1010
Type of Manuscript:  PAPER
Category: Fault Analysis, Testing and Verification
Keyword: 
fault analysis (K+1)-valued logic circuits, PLA, two-level, circuit, 
 Summary | Full Text:PDF