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IEICE Trans

Chi-Chang LIN

Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier
Jinn-Shyan WANG Pei-Yao CHANG Chi-Chang LIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/01/01
Vol. E95-C  No. 1  pp. 172-175
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
SRAM, subthreshold, variations, 
 Summary | Full Text:PDF