A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy Chao YANHongjun DAITianzhou CHEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/01/01 Vol. E95-DNo. 1pp. 38-45 Type of Manuscript: Special Section PAPER (Special Section on Trust, Security and Privacy in Computing and Communication Systems) Category: Trust Keyword: soft errors, fault tolerance, double execution, instruction reuse buffer, fast error correcting code,