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IEICE Trans

Celia LOPEZ

Generalized Reasoning Scheme for Redundancy Addition and Removal
Jose Alberto ESPEJO Luis ENTRENA Enrique San MILLAN Celia LOPEZ 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2665-2672
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
redundancy addition and removal, rewiring, logic synthesis, structural methods, 
 Summary | Full Text:PDF