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IEICE Trans

Benjamin STEFAN DEVLIN

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1319-1328
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self synchronous, fpga, pipeline alignment, low power, high throughput, dynamic logic, dual pipeline, 
 Summary | Full Text:PDF