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IEICE Trans

Bakhtiar Affendi ROSDI

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
Bakhtiar Affendi ROSDI Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2736-2742
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
pipelined circuits, multi-clock cycle paths, clock scheduling, delay balancing, 
 Summary | Full Text:PDF
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits
Bakhtiar Affendi ROSDI Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3435-3442
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
pipelined circuits, multi-clock cycle paths, clock scheduling, 
 Summary | Full Text:PDF