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IEICE Trans

Atsushi MATSUO

Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis
David CLARINO Naoya ASADA Atsushi MATSUO Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/04/01
Vol. E108-D  No. 4  pp. 320-329
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
relative-phase Toffoli gates (RTOF), circuit optimization, LUT, quantum circuit synthesis, 
 Summary | Full Text:PDF
A SAT Approach to the Initial Mapping Problem in SWAP Gate Insertion for Commuting Gates
Atsushi MATSUO Shigeru YAMASHITA Daniel J. EGGER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/11/01
Vol. E106-A  No. 11  pp. 1424-1431
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
quantum compiler, quantum circuit, SWAP strategy, initial mapping, 
 Summary | Full Text:PDF
Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits
Atsushi MATSUO Yudai SUZUKI Ikko HAMAMURA Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/11/01
Vol. E106-D  No. 11  pp. 1772-1782
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
VQE algorithm, optimization problem, problem-specific parameterized quantum circuit, 
 Summary | Full Text:PDF
An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement
Atsushi MATSUO Wakaki HATTORI Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/02/01
Vol. E106-A  No. 2  pp. 124-132
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
quantum circuit, Mixed-Polarity Multiple-Control Toffoli (MPMCT) gate, nearest neighbor architecture (NNA), 
 Summary | Full Text:PDF