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IEICE Trans

Atsushi KUMITA

Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method
Hideki ASAI Atsushi KUMITA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/10/25
Vol. E71-E  No. 10  pp. 962-964
Type of Manuscript:  LETTER
Category: Numerical Calculation and Mathematical Programming
Keyword: 
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