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IEICE Trans

Akira ONO

Interdigital and Multi-Via Structures for Mushroom-Type Metasurface Reflectors
Taisei URAKAMI Tamami MARUYAMA Shimpei NISHIYAMA Manato KUSAMIZU Akira ONO Takahiro SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2024/02/01
Vol. E107-B  No. 2  pp. 309-320
Type of Manuscript:  PAPER
Category: Antennas and Propagation
Keyword: 
metasurface, reflector, interdigital, multi-via, ray tracing, electromagnetic field simulation, 
 Summary | Full Text:PDF
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical test, built-in test circuit, open defect, interconnect test, design for testability, 
 Summary | Full Text:PDF
A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs
Keiichi KOIKE Kenji KAWAI Akira ONOZAWA Yuichiro TAKEI Yoshiji KOBAYASHI Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1578-1585
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
Si bipolar, ECL, standard cell, CAD, SDH, 
 Summary | Full Text:PDF
A Balanced-Mesh Clock Routing Technique for Performance Improvement
Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8  pp. 1489-1495
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LSI, CAD, layout design, clock skew, partitioning, routing, MPEG2, 
 Summary | Full Text:PDF
Power and Timing Optimization for ECL LSIs in Post-Layout Design
Akira ONOZAWA Hitoshi KITAZAWA Kenji KAWAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/06/25
Vol. E79-A  No. 6  pp. 892-899
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LSI CAD, ECL, power, delay, non-linear optimization, 
 Summary | Full Text:PDF