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IEICE Trans

Akinori SHIBAYAMA

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier
Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 630-638
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SRAM, low-voltage, wide-voltage, SoC, 
 Summary | Full Text:PDF