Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM

Tomohiro KORIKAWA  Akio KAWABATA  Fujun HE  Eiji OKI  

Publication:   IEICE TRANSACTIONS on Communications
Publicized: 2020/08/06
DOI: 10.1587/transcom.2020EBP3017
Type of Manuscript: PAPER
Full Text: PDF(1.2MB)