FPGA-based Annealing Processor with Time-division Multiplexing

Kasho YAMAMOTO  Masayuki IKEBE  Tetsuya ASAI  Masato MOTOMURA  Shinya TAKAMAEDA-YAMAZAKI  

Publication:   IEICE TRANSACTIONS on Information and Systems
Publicized: 2019/09/20
DOI: 10.1587/transinf.2019PAP0002
Full Text: PDF(2.4MB)