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Clock Recovery Circuit with Wideband Input Bitrate Range
Tsukasa IDA Tomoyuki TANAKA Satoshi NAKAO Toshimasa MATSUOKA Kenji TANIGUCHI
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2008/06/01
Online ISSN: 1881-0217
Print ISSN: 1345-2827
Type of Manuscript: PAPER
clock recovery circuit, oversampling, PFD,
Full Text(in Japanese): PDF(852.7KB)
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We propose a clock recovery circuit covering a wide range of input bitrate. The circuit implements VCO osillating at the input bitrate multiplied by OSR (over-sampling ratio) and PFD (phase/frequency detector) driven at the VCO clock rate. Under the data sequence with a given maximum CID (Consecutive Identical Digits) length, simulation results proved that the PFD to monitor CID length prevents the circuit from locking at a false frequency. Maximum CID length and OSR causes nonidealities of the circuit, where higher OSR leads to better maximum absolute phase error and higher maximum CID length demands smaller allowable jitter generation. Numerical simulation revealed that the proposed circuit locks at the frequcency associated with input bitrate of 100 k10 Mbit/s even if the initial frequencies of the VCO are far from the final locked one.