Proposal of Stacked Type Fe-FET Combinational Circuit / Memory for Its Evaluation Results for Non-volatile Sequential Circuits with BiCS Technology

Tomohiro YOKOTA  Shigeyoshi WATANABE  

Publication
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)   Vol.J100-C   No.10   pp.510-518
Publication Date: 2017/10/01
Online ISSN: 1881-0217
Type of Manuscript: PAPER
Category: 
Keyword: 
NAND type memory,  BiCS technology,  Fe-FET,  stacked structure,  sequential circuit,  combinational circuit,  non-volatile,  

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Summary: 
Vertical stacked type Fe-FET combinational circuit/memory for its evaluation results for non-volatile sequential circuits with BiCS technology has been newly proposed. In this scheme conventional flip flop circuit which uses more than 20 Fe-FETs has been successfully replaced by the only one Fe-FET stacked on the combinational circuit. As a result, more than X20 cost performance defined by (fabrication cost) * (cycle time for read/erase/program operation) can be successfully realized compared with that of conventional flip circuit scheme. The proposed scheme is promising candidate for realizing high cost performance non-volatile sequential circuit.