Exploratory Research of Intelligent Integrated Systems-Integration of Intelligence in a Chip-

Michitaka KAMEYAMA  

C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)   Vol.J100-C   No.10   pp.457-464
Publication Date: 2017/10/01
Online ISSN: 1881-0217
Type of Manuscript: INVITED PAPER (Special Section on IEICE 100th-Anniversary Historical Review on Electronics for Communication)
VLSI computing,  novel VLSI architecture,  real-world intelligent system,  algorithm selection,  reconfigurable VLSI,  

Full Text(in Japanese): FreePDF(3.7MB)

The exploratory research history of intelligent integrated systems is presented. Such a research stream contributes to development of intelligent systems for real-world applications. A computing platform for real-world intelligent systems is desired to contribute to low-cost implementation as well as high-quality and high-performance processing. High-performance, low-power and low-cost implementation is important for the industrial products, so that genetic hardware/software universal platform for almost all real-world intelligent systems is required to be developed. Novel reconfigurable VLSI architectures are presented which include an intra-chip packet routing scheme to reduce the size of the configuration memory, fine-grain power gating with asynchronous control to achieve low power, a multi-context switching scheme using a floating-gate-MOS functional pass gate, and multiple-valued signaling.