Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Hideki ANDO  Ryota SHIOYA  

IEICE TRANSACTIONS on Information and Systems   Vol.E99-D    No.2    pp.341-350
Publication Date: 2016/02/01
Publicized: 2015/11/12
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2015EDP7325
Type of Manuscript: PAPER
Category: Computer System
microprocessor,  superscalar processor,  memory-level parallelism,  instruction-level parallelism,  power consumption,  

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Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memory-intensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.