For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Fast Quantum Computer Simulator Based on Register Reordering
Masaki NAKANISHI Miki MATSUYAMA Yumi YOKOO
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Online ISSN: 1745-1361
Type of Manuscript: PAPER
Category: Computer System
quantum computer simulator, hardware implementation, register reordering,
Full Text: PDF(568.7KB)>>
Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.