A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Yuan HE  Masaaki KONDO  Takashi NAKADA  Hiroshi SASAKI  Shinobu MIWA  Hiroshi NAKAMURA  

IEICE TRANSACTIONS on Information and Systems   Vol.E99-D   No.12   pp.2881-2890
Publication Date: 2016/12/01
Publicized: 2016/08/24
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2016PAP0026
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Networks-on-Chip,  performance,  energy efficiency,  optimization,  selection,  

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Networks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.