Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing

Zhou JIANG  Guiming LUO  Kele SHEN  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.9   pp.1071-1079
Publication Date: 2016/09/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.1071
Type of Manuscript: PAPER
Category: Electronic Circuits
scan test,  scan segmentation,  lower power testing,  complex networks clustering,  design for testability,  at-speed testing,  

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The scan segmentation method is an efficient solution to deal with the test power problem; However, the use of multiple capture cycles may cause capture violations, thereby leading to fault coverage loss. This issue is much more severe in at-speed testing. In this paper, two scan partition schemes based on complex networks clustering ara proposed to minimize the capture violations without increasing test-data volume and extra area overhead. In the partition process, we use a more accurate notion, spoiled nodes, instead of violation edges to analyse the dependency of flip-flops (ffs), and we use the shortest-path betweenness (SPB) method and the Laplacian-based graph partition method to find the best combination of these flip-flops. Beyond that, the proposed methods can use any given power-unaware set of patterns to test circuits, reducing both shift and capture power in at-speed testing. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed methods.