A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

Haruki MORI  Yohei UMEKI  Shusuke YOSHIMOTO  Shintaro IZUMI  Koji NII  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.8   pp.901-908
Publication Date: 2016/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.901
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
image memory,  multi-port SRAM,  8T,  FD-SOI,  28-nm,  majority logic,  

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This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.