HyDRA: Hybrid Dynamically Reconfigurable Architecture for DSP Applications

Abdulfattah M. OBEID  Syed Manzoor QASIM  Mohammed S. BENSALEH  Abdullah A. ALJUFFRI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C    No.7    pp.866-877
Publication Date: 2016/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.866
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
coarse-grained,  digital signal processing (DSP),  fine-grained,  hybrid,  reconfigurable architecture,  

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Summary: 
Reconfigurable architectures have emerged as an optimal choice for the hardware realization of digital signal processing (DSP) algorithms. Reconfigurable architecture is either fine-grained or coarse-grained depending on the granularity of reconfiguration used. The flexibility offered by fine-grained devices such as field programmable gate array (FPGA) comes at a significant cost of huge routing area, power consumption and speed overheads. To overcome these issues, several coarse-grained reconfigurable architectures have been proposed. In this paper, a scalable and hybrid dynamically reconfigurable architecture, HyDRA, is proposed for efficient hardware realization of computation intensive DSP algorithms. The proposed architecture is greatly influenced by reported VLSI architectures of a variety of DSP algorithms. It is designed using parameterized VHDL model which allows experimenting with a variety of design features by simply modifying some constants. The proposed architecture with 8×8 processing element array is synthesized using UMC 0.25µm and LF 150nm CMOS technologies respectively. For quantitative evaluation, the architecture is also realized using Xilinx Virtex-7 FPGA. The area and timing results are presented to provide an estimate of each block of the architecture. DSP algorithms such as 32-tap finite impulse response (FIR) filters, 16-point radix-2 single path delay feedback (R2SDF) fast fourier transform (FFT) and R2SDF discrete cosine transform (DCT) are mapped and routed on the proposed architecture.