A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications

Nobutaro SHIBATA  Yoshinori GOTOH  Takako ISHIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.6   pp.717-726
Publication Date: 2016/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.717
Type of Manuscript: PAPER
Category: Integrated Electronics
10T type,  bitline capacitance,  CMOS,  gate array,  high speed,  low power,  memory-oriented base cell,  shared contact,  two-port SRAM,  

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Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-µm low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mVpp, and so we successfully reduced the required read bitline signal from 250 to 70 mVpp. With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25°C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.