Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture

Yo-Hao TU  Jen-Chieh LIU  Kuo-Hsing CHENG  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.6   pp.655-658
Publication Date: 2016/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.655
Type of Manuscript: BRIEF PAPER
static-phase-error,  delay-locked-loop,  frequency multiplier,  edge-combiner,  time amplifier,  

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This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM.