A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators

Sang-Min PARK  Yeon-Ho JEONG  Yu-Jeong HWANG  Pil-Ho LEE  Yeong-Woong KIM  Jisu SON  Han-Yeol LEE  Young-Chan JANG  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.6   pp.651-654
Publication Date: 2016/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.651
Type of Manuscript: BRIEF PAPER
asynchronous successive approximation register,  analog-to-digital converter,  meta-stability detector,  replica comparator,  

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A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.