A Low-Noise Dynamic Comparator for Low-Power ADCs

Yoshihiro MASUI  Kotaro WADA  Akihiro TOYA  Masaki TANIOKA  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.5   pp.574-580
Publication Date: 2016/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.574
Type of Manuscript: PAPER
Category: Electronic Circuits
dynamic comparator,  offset voltage,  low-noise,  low-power,  analog-to-digital convertor,  

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We propose a low-noise and low-power dynamic comparator with an offset calibration circuit for Low-Power ADCs. The proposed comparator equips the control circuit in order to switching the comparison accuracy and the current consumption. When high accuracy is not required, current consumption is reduced by allowing the noise increase. Compared with a traditional dynamic comparator, the proposed architecture reduced the current consumption to 78% at 100MHz operating and 1.8V supply voltage. Furthermore, the offset voltage is corrected with minimal current consumption by controlling the on/off operation of the offset calibration circuit.