A Noise-Robust Positive-Feedback Floating-Gate Logic

Luis F. CISNEROS-SINENCIO  Alejandro DIAZ-SANCHEZ  Jaime RAMIREZ-ANGULO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.4   pp.452-457
Publication Date: 2016/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.452
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
FGMOS logic,  differential logic,  digital integrated circuits,  multiple input floating gate MOS transistors,  

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Summary: 
Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.