An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis

Pil-Ho LEE  Yu-Jeong HWANG  Han-Yeol LEE  Hyun-Bae LEE  Young-Chan JANG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.4   pp.440-443
Publication Date: 2016/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.440
Type of Manuscript: BRIEF PAPER
Category: 
Keyword: 
on-chip monitoring circuit,  chip-to-chip interface,  analog-to-digital converter,  phase-locked loop-based frequency synthesizer,  sub-sampling,  

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Summary: 
An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.