A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme

Nobutaro SHIBATA  Takako ISHIHARA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.2   pp.316-330
Publication Date: 2016/02/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.316
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
4-way set-associative,  cache-tag,  CMOS,  directed graph,  dual-rail wordline,  FD-SOI,  I/O-separated memory cell,  LRU,  NRZ-type write-enable signal,  SIMOX,  SRAM,  

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Summary: 
Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.