Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems

Youngjoo LEE  Jaehwan JUNG  In-Cheol PARK  

IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.2   pp.293-301
Publication Date: 2016/02/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.293
Type of Manuscript: PAPER
Category: Electronic Circuits
energy-efficient design,  forward error-correction,  NAND flash memory,  VLSI designs,  

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This paper presents a novel low-power decoder architecture for the (36420, 32778) binary LDPC code targeting energy-efficient NAND-flash-based mobile devices. The proposed energy-scalable decoding algorithm reduces the operating bit-width of decoding function units at the early-use stage where the channel condition is good enough to lower the precision of computation. Based on a flexible adder structure, the decoding energy of the proposed LDPC decoder can be reduced by freezing the unnecessary parts of hardware resources. A prototype 4KB LDPC decoder is designed in a 65nm CMOS technology, which achieves an average decoding throughput of 8.13Gb/s with 1.2M equivalent gates. The power consumption of the decoder ranges from 397mW to 563mW depending on operating conditions.