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25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores
Kenichiro YASHIKI Toshinori UEMURA Mitsuru KURIHARA Yasuyuki SUZUKI Masatoshi TOKUSHIMA Yasuhiko HAGIHARA Kazuhiko KURATA
IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Online ISSN: 1745-1353
Type of Manuscript: INVITED PAPER (Special Section on Recent Advances in Photonics Technologies and Their Applications)
Si photonics, low-power-consumption, small footprint, high density interface, I/O bottleneck,
Full Text: FreePDF(3.6MB)
Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.