25-Gbps/ch Error-Free Operation over 300-m MMF of Low-Power-Consumption Silicon-Photonics-Based Chip-Scale Optical I/O Cores

Kenichiro YASHIKI  Toshinori UEMURA  Mitsuru KURIHARA  Yasuyuki SUZUKI  Masatoshi TOKUSHIMA  Yasuhiko HAGIHARA  Kazuhiko KURATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.2   pp.148-156
Publication Date: 2016/02/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.148
Type of Manuscript: INVITED PAPER (Special Section on Recent Advances in Photonics Technologies and Their Applications)
Category: 
Keyword: 
Si photonics,  low-power-consumption,  small footprint,  high density interface,  I/O bottleneck,  

Full Text: FreePDF


Summary: 
Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.