A 24 mW 5.7 Gbps Dual Frequency Conversion Demodulator for Impulse Radio with the First Sidelobe

Kaoru KOHIRA  Naoki KITAZAWA  Hiroki ISHIKURO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E99-C   No.10   pp.1164-1173
Publication Date: 2016/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E99.C.1164
Type of Manuscript: Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
Category: 
Keyword: 
clock recovery,  impulse radio,  UWB,  sidelobe,  

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Summary: 
This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.