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Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation
Takuya HIRATA Ryuta NISHINO Shigetoshi NAKATAKE Masaya SHIMOYAMA Masashi MIYAGAWA Ryoichi MIYAUCHI Koichi TANNO Akihiro YAMADA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
instrumentation amplifier, layout-dependent manufacturability, analog layout, matching layout,
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This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of an input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC-offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.