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LayerAware 3DIC Partitioning for AreaOverhead Reduction Considering the Power of Interconnections and Pads
YungHao LAI YangLang CHANG JyhPerng FANG Lena CHANG Hirokazu KOBAYASHI
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E99A
No.6
pp.12061215 Publication Date: 2016/06/01
Online ISSN: 17451337
DOI: 10.1587/transfun.E99.A.1206
Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: 3DIC, TSV, partitioning, areaoverhead reduction, power consumption,
Full Text: PDF(2.8MB)>>
Summary:
Throughsilicon vias (TSV) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for threedimensional (3D) integrated circuit (IC) technology. Several studies have investigated the placement and routing in 3D ICs, but not much has focused on circuit partitioning for 3D stacking. However, with the scaling trend of CMOS technology, the influence of the area of I/O pads, power/ground (P/G) pads, and TSVs should not be neglected in 3D partitioning technology. In this paper, we propose an iterative layeraware partitioning algorithm called EXiLap, which takes into account the area of I/O pads, P/G pads, and TSVs for area balancing and minimization of intertier interconnections in a 3D structure. Minimizing the quantity of TSVs reduces the total silicon die area, which is the main source of recurring costs during fabrication. Furthermore, estimations of the number of TSVs and the total area are somewhat imprecise if P/G TSVs are not taken into account. Therefore, we calculate the power consumption of each cell and estimate the number of P/G TSVs at each layer. Experimental results show that, after considering the power of interconnections and pads, our algorithm can reduce areaoverhead by ~39% and area standard deviation by ~69%, while increasing the quantity of TSVs by only 12%, as compared to the algorithm without considering the power of interconnections and pads.

