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A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology
Yu HOU Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Op-amp free, SAR, VCO, hybrid, 1-1 MASH ADC,
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This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.