Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

Cheng-Yu HAN  Yu-Ching LI  Hao-Tien KAN  James Chien-Mo LI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E99-A   No.12   pp.2320-2327
Publication Date: 2016/12/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E99.A.2320
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
IR-drop,  power-supply-noise,  timing analysis,  testing,  

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SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.