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FPGA Hardware with Target-Reconfigurable Object Detector
Yoshifumi YAZAWA Tsutomu YOSHIMI Teruyasu TSUZUKI Tomomi DOHI Yuji YAMAUCHI Takayoshi YAMASHITA Hironobu FUJIYOSHI
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/09/01
Online ISSN: 1745-1361
Type of Manuscript: Special Section PAPER (Special Section on Optimization and Learning Algorithms of Small Embedded Devices and Related Software/Hardware Implementation)
dynamic reconfiguration of detection target, object detection, FPGA,
Full Text: PDF(1.7MB)>>
Much effort has been applied to research on object detection by statistical learning methods in recent years, and the results of that work are expected to find use in fields such as ITS and security. Up to now, the research has included optimization of computational algorithms for real-time processing on hardware such as GPU's and FPGAs. Such optimization most often works only with particular parameters, which often forfeits the flexibility that comes with dynamic changing of the target object. We propose a hardware architecture for faster detection and flexible target reconfiguration while maintaining detection accuracy. Tests confirm operation in a practical time when implemented in an FPGA board.