A Multidimensional Configurable Processor Array — Vocalise

Jiang LI  Yusuke ATSUMARI  Hiromasa KUBO  Yuichi OGISHIMA  Satoru YOKOTA  Hakaru TAMUKOH  Masatoshi SEKINE  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E98-D   No.2   pp.313-324
Publication Date: 2015/02/01
Publicized: 2014/10/27
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2014EDP7219
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
FPGA array,  scalable,  hw/sw complex,  poisson equation,  distributed computing,  HPC,  

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Summary: 
A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted dimensionality and network topologies for different applications. We provide a fast and flexible circuit configuration method for FPGAs of a multi-dimensional FPGA array. To demonstrate the effectiveness of the proposed method, we assess performance and power consumption of a circuit that calculated 3D Poisson equations using the finite difference method.