Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD

Bing XU  Shouyi YIN  Leibo LIU  Shaojun WEI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E98-D   No.2   pp.243-251
Publication Date: 2015/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2014RCP0004
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
loop mapping,  software pipelining,  Dual-VDD,  low power,  Graph Minor,  

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Summary: 
Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.