Battery-Aware Loop Nests Mapping for CGRAs

Yu PENG  Shouyi YIN  Leibo LIU  Shaojun WEI  

IEICE TRANSACTIONS on Information and Systems   Vol.E98-D   No.2   pp.230-242
Publication Date: 2015/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2014RCP0003
Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
reconfigurable computing,  loop nests,  polyhedral model,  energy consumption,  discharge duration,  

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Coarse-grained Reconfigurable Architecture (CGRA) is a promising mobile computing platform that provides both high performance and high energy efficiency. In an application, loop nests are usually mapped onto CGRA for further acceleration, so optimizing the mapping is an important goal for design of CGRAs. Moreover, obviously almost all of mobile devices are powered by batteries, how to reduce energy consumption also becomes one of primary concerns in using CGRAs. This paper makes three contributions: a) Proposing an energy consumption model for CGRA; b) Formulating loop nests mapping problem to minimize the battery charge loss; c) Extract an efficient heuristic algorithm called BPMap. Experiment results on most kernels of the benchmarks and real-life applications show that our methods can improve the performance of the kernels and lower the energy consumption.