A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications

Chia-Wen CHANG  Yuan-Hua CHU  Shyh-Jye JOU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.8   pp.882-891
Publication Date: 2015/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.882
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
all-digital phase-locked loop,  hierarchical digitally controlled oscillators,  low voltage,  low power,  fast lock-in,  low jitter,  

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Summary: 
This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5MF (MF = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm2. In near-threshold region (VDD = 0.36 V), the proposed ADPLL only dissipates 68.2 µW and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V VDD operation, the proposed ADPLL dissipates 404.2 µW at 400 MHz. The fast lock-in time of 4.489 µs and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.