IEICE Trans - SET-Tolerant Active Body-Bias Circuits in PD-SOI CMOS Technology

SET-Tolerant Active Body-Bias Circuits in PD-SOI CMOS Technology

YoungKyu JANG
Ik-Joon CHANG
Jinsang KIM

Publication
IEICE TRANSACTIONS on Electronics Vol.E98-C No.7 pp.729-733
Publication Date: 2015/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.729
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword:
active body bias, history effect, PD-SOI, SET,

Full Text: PDF>>

Summary:
PD-SOI (Partial Depleted Silicon On Insulator) process is a good candidate technology for space system designs, since it features excellent insulation to the silicon substrate compared to the conventional bulk CMOS process. However, the radioactive particles from the low earth orbit can causes single event transient (SET) or abrupt charge collection in a circuit node, leading to a logical error in space systems. Also, the side effects such as the history effect and the kink effect in PD-SOI technology cause the threshold voltage variation, degrading the circuit performance. We propose SET-tolerant PD-SOI CMOS logic circuits using a novel active body-bias scheme. Simulation results show that the proposed circuits are more effective to SET and the side effects as well.