Design of q-Parallel LFSR-Based Syndrome Generator

Seung-Youl KIM  Kyoung-Rok CHO  Je-Hoon LEE  

IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.7   pp.594-596
Publication Date: 2015/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.594
Type of Manuscript: BRIEF PAPER
error control code,  parallel architecture,  LFSR,  BCH,  

Full Text: PDF(450.4KB)>>
Buy this Article

This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.