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Design of q-Parallel LFSR-Based Syndrome Generator
Seung-Youl KIM Kyoung-Rok CHO Je-Hoon LEE
IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Online ISSN: 1745-1353
Type of Manuscript: BRIEF PAPER
error control code, parallel architecture, LFSR, BCH,
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This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.