Variation-Aware Flip Flop for DVFS Applications

YoungKyu JANG  Changnoh YOON  Ik-Joon CHANG  Jinsang KIM  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E98-C   No.5   pp.439-445
Publication Date: 2015/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E98.C.439
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
design-for-variability,  flip-flop,  PVT variation,  DVFS,  

Full Text: PDF>>
Buy this Article




Summary: 
Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.