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Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting
Katsuhiko UEDA Zuiko RIKUHASHI Kentaro HAYASHI Hiroomi HIKAWA
IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Online ISSN: 1745-1353
Type of Manuscript: PAPER
Category: Electronic Circuits
CMOS logic circuit, low power consumption, dynamic power consumption, majority voting, bus-invert coding,
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It is important to reduce the power consumption of complementary metal oxide semiconductor (CMOS) logic circuits, especially those used in mobile devices. A CMOS logic circuit consists of metal-oxide-semiconductor field-effect transistors (MOSFETs), which consume electrical power dynamically when they charge and discharge load capacitance that is connected to their output. Load capacitance mainly exists in wiring or buses, and transitions between logic 0 and logic 1 cause these charges and discharges. Many methods have been proposed to reduce these transitions. One novel method (called segmentation coding) has recently been proposed that reduces power consumption of CMOS buses carrying band-limited signals, such as audio data. It improves performance by employing dedicated encoders for the upper and lower bits of transmitted data, in which the transition characteristics of band-limited signals are utilized. However, it uses a conventional majority voting circuit in the encoder for lower bits, and the circuit uses many adders to count the number of 1s to calculate the Hamming distance between the transmitted data. This paper proposes segmentation coding with pseudo-majority voting. The proposed pseudo-majority voting circuit counts the number of 1s with fewer circuit resources than the conventional circuit by further utilizing the transition characteristics of band-limited signals. The effectiveness of the proposed method was demonstrated through computer simulations and experiments.